GMS30C2216 Datasheet, PDF (118/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

5-2
CHAPTER 5
processor clock is changed by simultaneously changing the processor clock
divider and the timer prescaler divider.
The TPR is initialized to bit 27=1, bits 26 and 23..16=0 on reset (from the
RTESET# pin or by a clock-Down reset), i.e. the processor starts with CPU clock =
XTAL1 clock, the prescaler divides by 2. During a Watchdog (IO3 Timer) Reset,
the TPR is preserved, This allows the use of the Watchdog as a controlled time-
out without losing the time base.
Bits 30..28, 25..24 and 15..0 are reserved and must be zero on a move to TPR.
Bits Name
31
LoadEnable
30..28
27..26 ClockDivider
25..24
23..16 TimerPrescaler
15..0
Description
1 = TPR update is de3layed until current prescaler time unit ends
0 = TPR update is performed immediately
Reserved
CPU Clock Divider Control
11 = CPU clock = XTAL1 clock / 2
10 = CPU clock = XTAL1 clock
01 = CPU clock = XTAL1 clock * 2
00 = CPU clock = XTAL1 clock * 4
Reserved
Timer Prescaler Division factor n
Range n = 0..255, Timer Prescaler divides by n+2
Reserved
Table 5.1: Memory Address Spaces
5.1.2 Timer Register TR
The TR is a 32-bit register that is incremented by one on each time unit modulo 2³². Its
content can be used as the lower word of a double-word integer, representing the time
inclusive date.
The TPR and the TR should be set only once on system initialization, whereby the
following instruction sequence must be observed strictly (interrupts must be locked out):
:
:
FETCH 4
ORI SR, $20
MOV TPR, Lx
ORI SR, $20
MOV TR, Ly
:
:
; set H-flag
; load prescaler register from local register x
; set H-flag
; load timer register from local register y
Note: The Fetch instruction is necessary to prevent insertion of idle cycles during the
prescripted instruction sequence.