GMS30C2216 Datasheet, PDF (159/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

BUS INTERFACE
6-43
6.10.7.4 DRAM Refresh (CAS before RAS Refresh)
CLK
Address Bus
undefined
RAS#
CAS#
RAS precharge time
1..4 cycles
RAS to CAS delay time CAS access
1..4 cycles
time
1..6 cycles
Figure 6.17: DRAM Refresh