GMS30C2216 Datasheet, PDF (119/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

TIMER
5-3
5.1.3 Timer Compare Register TCR
The content of the TCR is compared continuously with the content of the timer register TR.
An unsigned modulo comparison is performed according to:
result(31..0) := TR(31..0) - TCR(31..0)
On result(31) = 0, the TR is higher than or equal to the TCR.
When the timer interrupt is enabled (FCR(23) = 0) and the value in the TR is higher than
or equal to the value in the TCR, a timer interrupt is generated. This interrupt is cleared by
loading the TCR with a value higher than the current content of the TR.
Timer interrupts can be masked out by FCR(23) = 1; FCR(23) is set to one on Reset. The
timer interrupt disable bit FCR(23) does not affect the timer and compare function.
A delay time in the TCR is calculated according to the formula:
TCR := current content of TR + number of delay time units
The maximum number of delay time units allowed for this calculation is 2³¹-1.
For example:
TR(31..0)
= hex FFFF FF00
delay time units (= 1000) = hex 0000 03E8
TCR(31..0)
= hex 0000 02E8
Since the modulo comparison is an unsigned operation, only unsigned arithmetic must be
used for calculations with timer and timer compare values. Do not use the N or C flag to
test for the result of the comparison TR - TCR, use only result bit 31!
5.1.4 Power-Down Mode
When the power-down mode is entered, the execution pipeline of the processor is halted.
Only the logic for the timer, IO3 control modes, interrupt and refresh is being clocked, all
other clocks are disabled. The processor is temporarily activated for refresh and bus
arbitration cycles, no instructions are executed during these temporary clock cycles. The
processor resumes execution by any interrupt or on a reset.
Power-down mode can be entered by executing an I/O write instruction with address bits
A(27) and A(25..23) set to one and A(22) set to zero.
When power-down mode is entered via the I/O write instruction, the power-down mode
takes effect at the time when the I/O access is performed. Until this time, instruction
execution continues. To ensure that the power-down mode takes effect, the power-down
I/O access can be followed by a dummy load accesses (I/O or memory). A following
dependent instruction then waits until both I/O accesses are performed. Thus, instructions
following the MOV instruction are not executed until wakeup. Note that even though the
power-down request is an internal operation of the processor, bus grant must be given so
that the power-down I/O access can be performed.