GMS30C2216 Datasheet, PDF (128/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

6-12
CHAPTER 6
6.2.1 I/O Bus Control
With I/O addresses, address setup, access and bus hold time can be specified by bits in the
I/O address as follows:
25
21
15 13 12 11 10 9 8 7 5 4 3 2 0
Reserved (must be 0)
I/O Address and/or I/O Chip Select
GMS30C2216: 6 Bits
GMS30C2232: 10 Bits
I/O Register Address
Reserved for System Peripheral
Wait Enable
Peripheral Device Control Mode
0 = IORD# / IOWR# Strobe Control
1 = R/W# / Data Strobe Control
Address Setup Time before Read or Write Access
00 = 0 cycles
01 = 2 cycles
10 = 4 cycles
11 = 6 cycles
Access Time for Read or Write Access
000 = 2 cycles
001 = 4 cycles
010 = 6 cycles
011 = 8 cycles
100 = 10 cycles
101 = 12 cycles
110 = 14 cycles
111 = 16 cycles
Bus Hold Time after Read or Write Access
00 = 0 cycles
01 = 2 cycles
10 = 4 cycles
11 = 6 cycles
Reserved for Internal Use (must be 0)
Figure 6.1: I/O Bus Control
Reserved bits must always be supplied as zero when specifying an I/O address in a
program.