GMS30C2216 Datasheet, PDF (140/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

6-24
CHAPTER 6
6.7 Watchdog Compare Register WCR
Global register G24 is the watchdog compare register WCR. Only bits 15..0 are used, bits
31..16 are reserved, they must be zero on a move to the WCR. In the present version, bits
31..16 are read as zero. The WCR is used by the IO3 control modes (see section 6.8. IO3
Control Modes).
6.8 IO3 Control Modes
Additionally to the standard use like IO1 and IO2 (see section 6.9.3. Bus Signal
Description), there are special control modes in combination with the IO3 pin. These
control modes are specified by FCR(13) and FCR(12).
On all IO3 control modes, the watchdog compare register WCR must be set before the
control mode is specified in the FCR, otherwise the EqualFlag could be set erroneously.
The EqualFlag and the EventFlag are being cleared on all IO3 control modes by either
setting FCR(13) to one or a move to the watchdog compare register WCR.
6.8.1 IO3Standard Mode
FCR(13) = 1, FCR(12) = 1 specifies IO3Standard mode.
Standard use of IO3 without any additional IO3 control functions. See section 6.9.3. for
signals IO1..IO3.
6.8.2 Watchdog Mode
FCR(13) = 1, FCR(12) = 0 specifies Watchdog mode.
A Reset exception occurs when WCR(15..0) = TR(15..0). The standard use of IO3 is not
affected.
Processor Clock
Frequency
carry
TPR
TR
Timer Clock
Frequency
compare x
Reset Exception
WCR
Note: The WCR must be set before the IO3 control mode is determined by FCR(13..12) as
Watchdog mode.