GMS30C2216 Datasheet, PDF (251/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

Appendix A. Instruction Set Details
Floating-point Division (double precision)
A-79
FDIVD
Format:
LL format
15
OP-code
1100 0111
87
43
0
Ld-code
Ls-code
Ls-code encodes L0..L15 for Ls
Ld-code encodes L0..L15 for Ld
Notation:
FDIVD Ld, Ls
Description:
The destination operand (Ld//Ldf) is divided by the source operand (Ls//Lsf), the result is
placed in the destination register (Ld//Ldf) and all condition flags remain unchanged to
allow future concurrent execution.
The floating-point instructions comply with the ANSI/IEEE standard 754-1985. In the
present version, they are executed as Software instructions.
This instruction uses double-precision operands and it must not placed as delay instructions.
A floating-point Not a Number (NaN) is encoded by bits 30..19 = all ones in the operand
word containing the exponent; all other bits of the operand are ignored for differentiating a
NaN form a non-NaN.
This instruction can raise any of the exceptions Invalid Operation, Division by Zero,
Overflow, Underflow or Inexact.
Operation:
Ld//Ldf := Ld//Ldf / Ls//Lsf
Exceptions:
Invalid Operation, Division by Zero, Overflow, Underflow or Inexact.