GMS30C2216 Datasheet, PDF (279/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

Appendix A. Instruction Set Details
Invert
A-107
NOT
Format:
RR format
15
OP-code
0100 01
10 9 8 7
43
0
ds
Rd-code
Rs-code
s = 0: Rs-code encoded G0..G15 for Rs
s = 1: Rs-code encoded L0..L15 for Rs
d = 0: Rd-code encoded G0..G15 for Rd
d = 1: Rd-code encoded L0..L15 for Rd
Notation:
NOT Rd, Rs
Description:
The source operand (Rs) is placed bitwise inverted in the designation register and the Z
flag is set or cleared accordingly.
The source operand and the result are interpreted as bit-strings of 32 bits each.
Operation:
Rd := not Rs;
Z := Rd = 0;
Exceptions:
None.