GMS30C2216 Datasheet, PDF (38/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

1-18
CHAPTER 1
1.6 Memory Organization
The architecture provides a memory address space in the range of 0..2³² - 1
(0..4,294,967,295) 8-bit bytes (4GByte). Memory is implied to be organized as 32-bit
words. The following memory data types are available (see figure 3.12)
• Byte unsigned (unsigned 8-bit integer, bitstring or character)
• Byte signed (signed 8-bit integer, two's complement)
• Halfword unsigned (unsigned 16-bit integer or bitstring)
• Halfword signed (signed 16-bit integer, two's complement)
• Word (32-bit undedicated word)
• Double-Word (64-bit undedicated double-word)
Besides the memory address space, a separate I/O address space is provided. In the I/O
address space, only word and double-word data types are available.
Words and double-words must be located at word boundaries, that is, their most significant
byte must be located at an address whose two least significant bits are zero (...xx00).
Halfwords must be located at halfword boundaries, their most significant byte being
located at an address whose least significant bit is zero (...xx0). Bytes may be located at
any address.
The variable-length instructions are located as contiguous sequences of one, two or three
halfwords at halfword boundaries.
Memory- and I/O-accesses are pipelined to an implied depth of two addresses.
Note: All data is located high to low order at addresses ascending from low to high, that is,
the high order part of all data is located at the lower address (Big endian). This scheme
should also be used for the addressing of bit arrays. Though the most significant bit of a
word is numbered as bit position 31 for convenience of use, it should be assigned the bit
address zero to maintain consistent bit addressing in ascending order through word
boundaries.
31
8
4
0
24 23
9
5
1
16 15
10
6
2
Big Endian
87
11
7
3
Word
0 ^Address 31
8
11
4
7
0
3
24 23
10
6
2
16 15
9
5
1
87
8
4
0
Little Endian
Word
0 ^Address
8
4
0
Figure 1.11: Address of bytes within words: Big-endian and little endian alignment.