GMS30C2216 Datasheet, PDF (147/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

BUS INTERFACE
States Names
O ACT
I
INT1..INT4
O/I IO1..IO3
I
RESET#
O/Z BOOTW,
BOOTB
6-31
Use
Active as bus master. ACT is signaled high when GRANT# is
low and it is kept high during a current bus access. Since
GRANT# is asynchronous, ACT follows GRANT# with a delay
of 2..3 cycles. ACT is also kept high on a bus lock
(FCR(17) = 0) from the beginning of the first access after
FCR(17) is cleared to zero until the bus lock is released by
setting FCR(17) to one.
Note: When ACT transits from high to low, the address and data
bus are switched to three state (inactive). All bus control signals
marked O/Z are driven high and then switched to three state.
These signals are kept high by an on-chip resistor (ca. 1 MΩ)
tied on-chip to Vcc.
Interrupt Request. A signal of a specified level on any of the
INT1..INT4 interrupt request pins causes an interrupt exception
when the interrupt lock flag L is zero and the corresponding
INTxMask bit in FCR is not set. The INTxPolarity bits in FCR
specify the level of the INTx signals: INTxPolarity = 1 causes
an interrupt on a high input signal level, INTxPolarity = 0
causes an interrupt on a low input signal level. INT1..INT4 may
be signaled asynchronously to the clock; they are not stored
internally.
A transition of INT1..INT4 is effective after a minimum of three
cycles. The response time may be much higher depending on the
number of cycles to the end of the current instruction or the
number of cycles until the interrupt lock flag L is cleared.
Note: The signal level of INT1..INT4 can be inspected in
ISR(0)..ISR(4). Thus, with the corresponding INTxMask bit set,
INT1..INT4 can be used just as input signals.
General Input-Output. IO1..IO3 can be individually configured
via IOxDirection bits in the FCR as either input or output pins.
When configured as input, IO1..IO3 can be used like
INT1..INT4 for additional interrupt or input signals.
When configured as output, the IOxPolarity bit in FCR specifies
the output signal level. IOxPolarity = 1 specifies a high level,
IOxPolarity = 0 specifies a low level. IO1..IO3 are always
switched rail-to-rail regardless of the setting of MCR(25). An
output signal at IO1 or IO2 cannot cause an interrupt regardless
of the corresponding IOxMask bit; however, it can be inspected
as IOxLevel in ISR (e.g. for testing). IO3 can be used for
various control functions.
Reset processor. RESET# low resets the processor to the initial
state and halts all activity. RESET# must be low for at least two
cycles. On a transition from low to high, a Reset exception
occurs and the processor starts execution at the Reset entry. The
transition may occur asynchronously to the clock.
Input pins for selecting the data bus width for boot memory area
MEM3 (see section 6.1.1. Boot Width Selection).