GMS30C2216 Datasheet, PDF (157/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

BUS INTERFACE
6-41
6.10.7.2 EDO DRAM Single-Cycle Access
CLK
Address Bus
high order bits
Address Bus
low order bits
RAS#
valid
undefin
Row address
col. addr. col. addr.
CAS0#..CAS3#
RAS precharge time
1..6 cycles
RAS to CAS delay time CAS access CAS access
1..6 cycles
time
time
1..6 cycles 1..6 cycles
WE#
at read access
OE#
Data Bus
(read data)
WE#
at write access
OE#
Data Bus
(write data)
Figure 6.15: EDO DRAM Single-Cycle Access