GMS30C2216 Datasheet, PDF (208/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

A-36
Divide with Unsigned
Appendix A. Instruction Set Details
DIVU
Format:
RR format
15
OP-code
0000 10
10 9
d
87
s
Rd-code
43
0
Rs-code
s = 0: Rs-code encoded G0..G15 for Rs
s = 1: Rs-code encoded L0..L15 for Rs
d = 0: Rd-code encoded G0..G15 for Rd
d = 1: Rd-code encoded L0..L15 for Rd
Notation:
DIVU Rd, Rs
Description:
The double-word destination operand (dividend) is divided by the single-word source
operand (divisor), the quotient is placed in the low-order destination register (Rdf), the
remainder is placed in the high-order destination register (Rd) and the condition flags are
set or cleared according to the quotient.
A trap to Range Error occurs if the divisor is zero or the value of the quotient exceeds the
integer value range (quotient overflow). The result (in Rd//Rdf) is then undefined.
The dividend is an unsigned double-word integer, the devisor, the quotient and the
remainder are unsigned integers
The result is undefined if Rs denotes the same register as Rd or Rdf or if the PC or the SR
is denoted.
Operation:
If Rs = 0 or quotient overflow then
Rd//Rdf := undefined;
Z := undefined;, N := undefined;,
V :=1 trap -> Range Error
else
remainder Rd, quotient Rdf := (Rd//Rdf) / Rs;
Z := Rdf = 0
N := Rd(31), V:= 0;
Exceptions:
Quotient Overflow (Trap to a Range Error)
Division by Zero (Trap to a Range Error)