GMS30C2216 Datasheet, PDF (262/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

A-90
Load (displacement address mode)
Appendix A. Instruction Set Details
LDxx.D
Format:
RRdis format
15
OP-code 1001 00
eS
DD
87
43
0
ds
Rd-code
Rs-code
dis1
dis2
s = 0: Rs-code encodes G0..G15 for Rs, s = 1: Rs-code encodes L0..L15 for Rs
d = 0: Rd-code encodes G0..G15 for Rd, d = 1: Rd-code encodes L0..L15 for Rd
S : Sign bit of dis, e = 0: dis = 20S // dis1(range -4,096..4,095)
e = 1: dis = 4S // dis1 // dis2 (range -268,435,456...268,435,455)
DD: D-code, D13..D12 encode data types at memory instructions
Notation:
LDxx.D Rd, Rs, dis
Description:
The Load instruction of displacement address mode transfers data from the addressed
memory location, Rd plus a signed dis is used as an address, into a register Rs or a register
pair Rs//Rsf.
The sum of the contents of the destination register Rd plus a signed displacement dis is
used as an address into memory address space.
Rd may denote any register except the SR; Rd not denoting the SR differentiates this mode
from the absolute address mode.
Data type xx is with
BU: Byte unsigned HU: Halfword unsigned W: Word
BS: Byte singed HS: Halfword signed D: Double-word
Operation:
Rs := (Rd + dis)^;
[Rsf := (Rd + dis + 4)^;
Exceptions:
None.