GMS30C2216 Datasheet, PDF (117/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

TIMER
5-1
5. Timer and CPU Clock Modes
5.1 Overview
The on-chip timer is controlled via three registers:
Timer prescaler register TPR
G21
Timer register TR
G23
Timer compare register TCR
G22
G21..G23 can be addressed only via the high global flag H by a MOV or MOVI instruction.
The content of G21 (timer prescaler register) cannot be read.
The write-only TPR sets a carry flag C (overflow) when the value of the counter in TPR
equals to the content of TPR, and transfers carry flag C to the TR. When the TPR transfers
carry flag to the TR, TR increments by one on modulo 2³². Timer clock frequency is
determined by the content of TPR.
When the TR higers than or equals to the TCR, the timer interrupt is generated.
Processor Clock
Frequency
carry
TPR
TR
Timer Clock
Frequency
compare x
Timer Interrupt
TCR
Fig. 5.1 The block diagram of on-chip timer.
5.1.1 Timer Prescaler Register TPR
Global register G21 is the write-only Timer Prescaler Register TPR. The TPR adapts the
timer clock to different processor clock frequencies and controls the PLL clock output.
Bits 26 and 27 select the processor clock. Bits 23..16 determine the basic time unit
frequency of timer clock := frequency of processor clock divided by (n+2)
n is the value to be loaded into the TPR at the bit positions 23..16, it is calculated according
to the formula:
n = (time unit ∗ frequency of processor clock) - 2
Bit 31 determines the effect of a write to TPR. If bit 31 is 0, a write to TPR takes
effect immediately, the processor clock divider is changed and the timer prescaler
divider is reloaded. If bit 31 is 1, the processor clock divider and timer prescaler
divider update is delayed until the current basic time unit ends. At the end of the
current time unit, the processor clock divider and the timer prescaler divider are
updated with the new values. This allows keeping absolute timing even when the