GMS30C2216 Datasheet, PDF (269/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

Appendix A. Instruction Set Details
Mask
A-97
MASK
Format:
RRconst format
15
OP-code 0001 01
eS
87
43
0
ds
Rd-code
Rs-code
const1
cosnt2
s = 0: Rs-code encodes G0..G15 for Rs, s = 1: Rs-code encodes L0..L15 for Rs
d = 0: Rd-code encodes G0..G15 for Rd, d = 1: Rd-code encodes L0..L15 for Rd
S : Sign bit of dis, e = 0: const = 18S // const1 (range -16,384..16,383)
e = 1: const = 2S // const1 // const2 (range -1,073,741,824...1,073,741,823)
Notation:
MASK Rd, Rs, const
Description:
The result of a bitwise logical AND of the source operand and the immediate operand is
placed in the destination register and the Z flag is set or cleared accordingly.
All operands and the result are interpreted as bit-string of 32 bits each.
Operation:
Rs := Rd and const;
Z := Rd = 0;
Exceptions:
None.