GMS30C2216 Datasheet, PDF (29/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

ARCHITECTURE
1-9
1.2.2 Status Register SR, G1
G1 is the status register SR. Its content is updated by instruction execution. Besides this
implicit updating, the SR can also be addressed like a regular register (when H flag is set).
When addressed as source or destination operand, all 32 bits are used as an operand.
However, only bits 15..0 of a result can be placed in bits 15..0 of the SR, bits 31..16 of the
result are discarded and bits 31..16 of the SR remain unchanged. When SR addressed as
source operand, it represents 0x0 value. The full content of the SR is replaced only by the
Return Instruction. A result placed in the SR overrules any setting or clearing of the
condition flags as a result of an instruction.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FP
FL
ILC S P T
Frame Pointer
Trace-Mode Flag
Trace Pending Flag
Supervisor State Flag
Instruction-Length Code
Frame Length
Figure 1.6: Status Register SR (bits 31..16)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L FRM
FTE
I
HMV N ZC
Carry Flag
Zero Flag
Negative Flag
Overflow Flag
Cache-Mode Flag
High Global Flag
Reserved
Interrupt-Mode Flag
Floating-Point Trap Enable
Floating-Point Rounding Mode
Interrupt-Lock Flag
Figure 1.7: Status Register SR (bits 15..0)