GMS30C2216 Datasheet, PDF (135/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

BUS INTERFACE
6-19
6.4.1 MEMx Parity Disable
Bits 31..28 of the MCR control parity generation and parity check for each memory area.
The default setting is parity check disables. The appropriate MCR bit must be cleared to
enable the parity check for that memory area.
6.4.2 MEMx Wait Disable
Bit 26 of the MCR controls the wait pin function for the memory area MEM2. The default
setting is wait function disabled. The MCR bit must be cleared to enable the wait function
for the MEM2 memory area. When this function is enabled, the INT2/WAIT input of the
processor is used as wait pin. Any MEM2 memory access remains active as long as the
signal at the WAIT input is asserted (the WAIT input is sampled after the first three access
cycles of the memory access). The access will be terminated after the WAIT input becomes
disserted. Whether the input is low-asserted or high-asserted can be programmed via bit 26
of the Function Control Register FCR. A minimum access time of four cycles must be
specified for a memory area with the wait function enabled.
If the INT3/WAIT input is used as wait pin, bit 30 of the FCR (INT3Mask) should be set to
1 so that no interrupts are generated on the assertion of WAIT.
6.4.3 MEMx Byte Mode
Bit 23, 19, and 15 of the MCR control the byte write access mode for memory areas
MEM2, MEM1, and MEM0, respectively. The default setting is byte-write-strobe,
meaning that the signals WE0#..WE3# are used as write strobe signals for writing the
appropriate data byte to the external memory. When the MCR bit is cleared, the signals
WE0#..WE3# act as a byte enable signal and the general WE# signal must be used for
writing the data to the memory.
Note: Most SRAM chips with 16-bit or 32-bit wide data interface require a single write-
enable signal and dedicated enable signals for each byte. The setting MEMxByteMode = 0
is intended specifically for those types of memories.
6.4.4 Power Down
Bit 22 of the MCR controls the power-down mode. The default setting is processor active.
To switch the processor to power-down mode MCR(22) must be cleared. The switch to
power-down is initiated by a transition from MCR(22) = 1 to MCR(22) = 0; thus,
MCR(22) must be restored to one for at least one cycle before a new switch to power-down
mode can occur.
In power-down mode, only the logic for the timer, IO3Control modes, interrupt and refresh
is being clocked, all other clocks are disabled. The switch to power-down mode is delayed
until the memory pipeline is empty. The processor is activated temporarily for refresh and
bus arbitration cycles and is switched back to processor active by any interrupt or on Reset.
Note that MCR(22) is not switched back to one by an interrupt.
6.4.5 IRAM Refresh Test
Bit 20 of the MCR specifies the internal RAM (IRAM) refresh test. The default setting is
normal mode, MCR(20) = 0 specifies refresh test mode.