GMS30C2216 Datasheet, PDF (129/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

BUS INTERFACE
6-13
6.3 Bus Control Register BCR
Global register G20 is the write-only bus control register BCR. The BCR defines the
parameters (bus timing, refresh control, page fault and parity error disable) for accessing
external memory located in address spaces MEM0..MEM3.
All bits of the BCR are set to one on Reset. They are intended to be initialized according to
the hardware environment.
Bits Name
31..28 Mem3Access
27..24 Mem2Access
23
Mem1Hold
Description
Access time for address space MEM3
1111 = 16 clock cycles
1110 = 15 clock cycles
1101 = 14 clock cycles
1100 = 13 clock cycles
1011 = 12 clock cycles
1010 = 11 clock cycles
1001 = 10 clock cycles
1000 = 9 clock cycles
0111 = 8 clock cycles
0110 = 7 clock cycles
0101 = 6 clock cycles
0100 = 5 clock cycles
0011 = 4 clock cycles
0010 = 3 clock cycles
0001 = 2 clock cycles
0000 = 1 clock cycle
Access time for address space MEM2
1111 = 16 clock cycles
1110 = 15 clock cycles
1101 = 14 clock cycles
1100 = 13 clock cycles
1011 = 12 clock cycles
1010 = 11 clock cycles
1001 = 10 clock cycles
1000 = 9 clock cycles
0111 = 8 clock cycles
0110 = 7 clock cycles
0101 = 6 clock cycles
0100 = 5 clock cycles
0011 = 4 clock cycles
0010 = 3 clock cycles
0001 = 2 clock cycles
0000 = 1 clock cycle
Bus hold time code for address space MEM1
When BCR(22) = 1:
1 = 2 clock cycles
0 = 1 clock cycle
When BCR(22) = 0
1 = 1 clock cycle
0 = 0 clock cycles