GMS30C2216 Datasheet, PDF (289/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

Appendix A. Instruction Set Details
Shift Left (Double Word)
A-117
SHLD
Format:
LL format
15
OP-code
1000 1010
87
43
0
Ld-code
Ls-code
Ld-code encodes L0..L15 for Ld
Ls-code encodes L0..L15 for Ls
Notation:
SHLD Ld, Ls
Description:
The destination operand is shifted left by a number of bit positions specified by bits 4..0 of
the source operand as a shift by 0..31. The higher-order bits of the source operand are
ignored. The destination operand is interpreted as a signed or unsigned double-word
integer.
The Shift Left instruction inserts zeros in the vacated bit positions at the right.
The double-word Shift Left instruction executes in two cycles. The high-order operand in
Ld is shifted first. The result is undefined if Ls denotes the same register as Ld or Ldf.
Operation:
Ld//Ldf := Ld//Ldf << by Ls(4..0);
Z := Ld//Ldf = 0;
N := Ld(31);
C := undefined;
V := undefined;
Exceptions:
None.