GMS30C2216 Datasheet, PDF (27/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

ARCHITECTURE
1-7
1.2 Global Register Set
The architecture provides 32 global registers of 32bit each. These are:
G0
G1
G2
G3..G15
G16..G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28..G31
Program Counter PC
Status Register SR
Floating-point Exception Register FER
General purpose registers
Reserved
Stack Pointer SP
Upper stack Bound UB
Bus Control Register BCR (see section 6. Bus Interface)
Timer Prescaler Register TPR (see section 5. Timer and CPU Clock
Modes)
Timer Compare Register TCR (see section 5. Timer and CPU Clock
Modes)
Timer Register TR (see section 5. Timer and CPU Clock Modes)
Watchdog Compare Register WCR (see section 6. Bus Interface)
Input Status Register ISR (see section 6. Bus Interface)
Function Control Register FCR (see section 6. Bus Interface)
Memory Control Register MCR (see section 6. Bus Interface)
Reserved
Registers G0..G15 can be addressed directly by the register code (0..15) of an instruction.
Registers G18..G27 can be addressed only by a MOV or MOVI instruction with the high
global flag H set to 1.
(Example)
MOVI G2, 0x20
; G2 := 0x20 (set H flag)
MOV
G3, G19 ; G3 := G19 (G19 (UB) is copied to G3)