GMS30C2216 Datasheet, PDF (252/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

A-80
Fetch
Appendix A. Instruction Set Details
FETCH
Format:
Rn format
15
OP-code
1011 10
10 9 8 7
43
0
d
0
n
Rd-code
1 (G1 = SR)
n
d = 0: Rd-code encoded R0..R15 for Rd
d = 1: Rd-code encoded L0..L15 for Rd
n: Bit 8 // bits 3..0 encode n = 0..31
Notation:
FETCH Ld, Ls
Description:
The instruction execution is halted until a number of at least n/2 + 1 (n = 0, 2, 4, ..., 30)
instruction halfwords succeeding the Fetch instruction are prefetched in the instruction
cache. The number of n/2 is derived by using bits 4..1 of n, bit 0 of n must be zero.
The Fetch instruction must not be placed as a delay instruction; when the preceding branch
is taken, the prefetch is undefined.
The Fetch instruction shares the basic OP-code SETxx, it is differentiated by denoting the
SR for the Rd-code.
Operation:
FETCH 1 Wait until 1 instruction halfword is fetched
FETCH 2 Wait until 2 instruction halfwords are fetched
........
FETCH 16 Wait until 2 instruction halfwords are fetched
Exceptions:
None.