GMS30C2216 Datasheet, PDF (75/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

Instruction Set
3-13
3.5 Invert Instruction
The source operand is placed bitwise inverted in the destination register and the Z flag is
set or cleared accordingly.
The source operand and the result are interpreted as bitstrings of 32 bits each.
Format Notation
Operation
RR
NOT Rd, Rs
Rd := not Rs;
Z := Rd = 0;
3.6 Mask Instruction
The result of a bitwise logical AND of the source operand and the immediate operand is
placed in the destination register and the Z flag is set or cleared accordingly.
All operands and the result are interpreted as bitstrings of 32 bits each.
Format Notation
Operation
RRconst MASK Rd, Rs, const
Rd := Rs and const;
Z := Rd = 0;
Note: The Mask instruction may be used to move a source operand with bits partly masked
out by an immediate operand used as mask. The immediate operand const is constrained in
its range by bits 31 and 30 being either both zero or both one (see format RRconst). If
these bits are required to be different, the instruction pair MOVI, AND may be used
instead of MASK.