GMS30C2216 Datasheet, PDF (126/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

6-10
CHAPTER 6
6.1.3.1 DRAM Row Address Bits Multiplexing
Table 8.3 shows the DRAM row address bits multiplexing. The page size code is specified
in the Bus Control Register BCR. The gray fields denote the multiplexed DRAM row
address bits. The white fields denote the DRAM row address bits that are not
multiplexed.
Address Bus bits
31..16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Page Size
Code
0 (000₂)
1 (001₂)
2 (010₂)
3 (011₂)
4 (100₂)
5 (101₂)
6 (110₂)
7 (111₂)
DRAM Row Address Bits
31..16
31..16
31..16
31..16
31..16
31..16
31..16
31..16
29 27 25 23 21 19 17 28 26 24 22 20 18 16 £ - £ -
15 27 25 23 21 19 17 16 26 24 22 20 18 16 28 29
15 14 25 23 21 19 17 15 14 24 22 20 18 16 26 27
15 14 13 23 21 19 17 15 14 13 22 20 18 16 24 25
15 14 13 12 21 19 17 15 14 13 12 20 18 16 22 23
15 14 13 12 11 19 17 15 14 13 12 11 18 16 20 21
15 14 13 12 11 10 17 15 14 13 12 11 10 16 18 19
15 14 13 12 11 10 9 16 14 13 12 11 10 9 16 17
Table 6.3: DRAM Row Address Bits Multiplexing
Note: DRAM can only be connected to memory area MEM0. The address bit A0 of the
address bus is not used in case of a 16-bit bus size for memory area MEM0. The address
bits A1 and A0 of the address bus are not used in case of a 32-bit bus size for memory area
MEM0. In case of page size code 0, only a 32-bit bus size for memory area MEM0 can be
used. Memory area MEM0 is only selected, if address bits A31 and A30 of a memory
address are zero.