GMS30C2216 Datasheet, PDF (125/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

BUS INTERFACE
6-9
6.1.3 DRAM Bus Access
A DRAM access to the same DRAM page as addressed by the previous DRAM access is
executed as fast page mode access. See bus control register BCR(17..16) for the access
time and low-cycles of the CASx# signals. CAS0#..CAS3# signals enable the
corresponding memory bytes 0..3.
A RAS access occurs when the DRAM page is different from the previously accessed
DRAM page. The RAS# signal is switched to high for the number of specified precharge
cycles. The high-order row address bits are multiplexed to the bit positions of the low-
order column address bits according to the specified page size after the first bus cycle until
the end of the specified RAS-to-CAS delay cycles. After the RAS-to-CAS delay cycles,
the column address bits are available on the low-order bit positions and the CAS access
cycle begins.
The row address bits are available at the high-order bit positions for the whole DRAM
access. After a DRAM access, the addressed DRAM page is being available for fast page
mode accesses to the same page until either a new DRAM page is addressed, the processor
is released to another bus master for DMA or a DRAM refresh takes place.
Note: The multiplexed row address bits are not in any specific order.
DRAM Read and Write Cycle
(1) Write Cycle
Active word line→ TR: ON→ Load stored data to
bit line→ Data write
(2) Read Cycle
Word Line (Row Address Line)
Pass
Transister
Apply V_DD/2 to bit line→ Active word line→ Read
data
Capacitor
stored in capacitor
(3) Refresh (CAS before RAS)
CAS before RAS signal → Enter refresh mode → Store
original data to sense amplifier → Active word line → Refresh (data write)