GMS30C2216 Datasheet, PDF (61/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

Instruction General
2-13
Fetch instruction:
when the required number of instruction half-words is already prefetched in the
instruction cache: 1 cycle
otherwise
1 + (required number of half-words - number of half-words already prefetched)/2
* bus cycles per access
Memory word instructions, non-stack address mode:
1 cycle
Memory word instructions, stack address mode:
3 cycles
Memory double-word instructions:
2 cycles
For timing calculations, double-word memory instructions are treated like a sequence of
two single-word memory instructions.
Idle wait cycles are transparently inserted when a memory instruction has to wait for
execution because the two-stage address pipeline is full.
Instruction execution proceeds after the execution of a Load instruction until the data
requested is needed (that is, the register into which the data is to be loaded is addressed) by
a further instruction.
The cycles executed between the memory instruction cycle requesting the data and the first
cycle at which the data are available are called read latency cycles. These read latency
cycles can be filled with instructions that do not need the requested data. When, after the
execution of these optional fill instruction cycles, the data is still not available in the cycle
needing it, idle wait cycles are inserted until the data is available. The idle wait cycles are
inserted transparently to the program by an on-chip hardware interlock. The read latency
is:
On an IRAM access:
read latency = 1 cycle
On a non-RAS external memory or I/O access:
read latency = address setup cycles + access cycles + 1
On a RAS memory access:
read latency = RAS precharge cycles + RAS to CAS delay cycles +
access cycles + 1
Additional cycles are also inserted and add to the latency when the address pipeline is
congested, these cycles must then also be taken into calculation.
A switch from an external memory or I/O read access to an immediately succeeding writes
access inserts one additional bus cycle.
Extended DSP instructions:
The instruction issue time is always 1 cycle. After the issue of an Extended DSP
instruction, execution of non-Extended-DSP instructions proceeds while the Extended DSP
instruction is executed in the multiply/accumulate unit (using separate resources). Latency
cycles are defined as the interval between instruction issue and the result being available in
the register G15 or register pair G14//G15. The latency cycles indicate as well the number
of cycles available for instructions not using the result that can be inserted between the