GMS30C2216 Datasheet, PDF (175/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

Appendix A. Instruction Set Details
ADD with carry
A-3
ADDC
Format:
RR format
15
OP-code
0101 00
10 9
d
87
s
Rd-code
43
0
Rs-code
s = 0: Rs-code encoded G0..G15 for Rs
s = 1: Rs-code encoded L0..L15 for Rs
d = 0: Rd-code encoded G0..G15 for Rd
d = 1: Rd-code encoded L0..L15 for Rd
Notation:
ADDC Rd, Rs
ADDC Rd, C (when SR is denoted as a Rs)
Description:
The source operand (Rs) + C is added to the destination operand (Rd), the result is placed
in the destination register (Rd) and the condition flag are set or cleared accordingly.
Both operands and the result are interpreted as either all signed or all unsigned integers.
When the SR is denoted as a source operand, carry flag C is added instead of the SR.
Operation:
When Rs is not SR
Rd := Rd + Rs + C;
Z := Z and (Rd=0);
N := Rd(31);
V := overflow;
C := carry;
When Rs is SR
Rd := Rd + C;
Z := Z and (Rd=0);
N := Rd(31);
V := overflow;
C := carry;
Exceptions:
None.