GMS30C2216 Datasheet, PDF (39/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

ARCHITECTURE
1-19
Figure 1.12 shows the location of data and instructions in memory relative to a binary
address n = ...xxx00 (x = 0 or 1). The memory organization is big-endian.
31
Byte n
Byte n + 1
Byte n + 2
0
Byte n + 3
Halfword n
Halfword n + 2
Byte n
Byte n + 1
Halfword n + 2
Halfword n
Byte n + 2
Byte n + 3
Word n
High-Order Word n of Double-Word
Low-Order Word n + 4 of Double-Word
1st Instruction Halfword
3rd Instruction Halfword (opt.)
2nd Instruction Halfword (opt.)
Preceding Instruction
2nd Instruction Halfword (opt.)
1st Instruction Halfword
3rd Instruction Halfword (opt.)
Figure 1.12: Memory Organization
At all data types, the most significant bit is located at the higher and the least significant bit
at the lower bit position.