GMS30C2216 Datasheet, PDF (69/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

Instruction Set
3-7
3.1.2 Load Instructions
The Load instructions transfer data from the addressed memory location into a register Rs
or a register pair Rs//Rsf.
In the case of data types word and double-word, one or two words are read from memory
and transferred unchanged into Rs or Rs//Rsf respectively.
In the case of byte and half-word data types, up to one word (depending on bus size) is
read from memory, the byte or half-word addressed by bits one and zero or bit one of the
memory address respectively is extracted, right adjusted, expanded to 32 bits and placed in
Rs. Unsigned bytes and half-words are expanded by leading zeros; signed bytes and half-
words are expanded by leading sign bits.
Execution of a Load instruction enters the register address of Rs, memory address bits one
and zero and a code for the data type into the load pipeline, places the memory address
onto the address bus and starts a memory cycle. A double-word Load instruction enters the
register address of Rsf and the same control information into the load pipeline as a second
entry, places the memory address incremented by four onto the address bus and starts a
second memory cycle.
After execution of a Load instruction, the next instructions are executed without waiting
for the data to be loaded. A wait is enforced only if an instruction uses a register whose
register address is still in the load pipeline. The data read from memory is placed in the
register whose register address is at the head of the load pipeline, its pipeline entry is then
deleted.
At memory load instruction Rs denotes the load destination register to load data from
memory, IO or stack and Rd denotes the load source register.
Rs must not denote the PC, the SR, G14 or G15; these registers cannot be loaded from memory.
Format
LR
LR
RRdis
RRdis
RRdis
RRdis
Notation
LDxx.R Ld, Rs
LDxx.P Ld, Rs
LDxx.D Rd, Rs, dis
LDxx.A 0, Rs, dis
LDxx.IOD Rd, Rs, dis
LDxx.IOA 0, Rs, dis
Operation
Data Type xx
Rs := Ld^;
[Rsf := (Ld + 4)^;]
-- register address mode
W,D
Rs := Ld^; Ld := Ld + size;
-- size = 4 or 8
[Rsf := (old Ld + 4)^;]
-- postincrement address mode
W,D
Rs := (Rd + dis)^;
[Rsf := (Rd + dis + 4)^;]
-- displacement address mode
BU,BS,HU,HS,W,D
Rs := dis^;
[Rsf := (dis + 4)^;]
-- absolute address mode
BU,BS,HU,HS,W,D
Rs := (Rd + dis)^;
[Rsf := (Rd + dis + 4)^;]
-- I/O displacement address mode
W,D
Rs := dis^;
[Rsf := (dis + 4)^;]
-- I/O absolute address mode
W,D