GMS30C2216 Datasheet, PDF (293/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

Appendix A. Instruction Set Details
Shift Right (Unsigned Double Word)
A-121
SHRD
Format:
LL format
15
OP-code
1000 0010
87
43
0
Ld-code
Ls-code
Ld-code encodes L0..L15 for Ld
Ls-code encodes L0..L15 for Ls
Notation:
SHRD Ld, Ls
Description:
The destination operand is shifted right by a number of bit positions specified by bits 4..0
of the source operand as a shift by 0..31. The higher-order bits of the source operand are
ignored. The destination operand is interpreted as a unsigned double-word integer.
The Shift Right instruction inserts zeros in the vacated bit positions at the left.
The double-word Shift Right instruction executes in two cycles. The high-order operand in
Ld is shifted first. The result is undefined if Ls denotes the same register as Ld or Ldf.
Operation:
Ld//Ldf := Ld//Ldf >> by Ls(4..0);
Z := Ld//Ldf =0;
N := Ld(31);
C := last bit shifted out is "one"
Exceptions:
None.