GMS30C2216 Datasheet, PDF (85/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

Instruction Set
3-23
3.15 Shift Right Instructions
The destination operand is shifted right by a number of bit positions specified
at SARI, SARDI, SHRI, SHRDI by n = 0..31 as a shift by 0..31.
at SAR, SARD, SHR, SHRD by bits 4..0 of the source operand as a shift by 0..31.
The higher-order bits of the source operand are ignored.
The destination operand is interpreted
at SAR and SARI as a signed integer;
at SARD and SARDI as a signed double-word integer;
at SHR and SHRI as a bitstring of 32 bits or as an unsigned integer;
at SHRD and SHRDI as a double-word bitstring of 64 bits or as an unsigned
double-word integer.
All Shift Right instructions that interpret the destination operand as signed insert sign bits,
all others insert zeros in the vacated bit positions at the left.
The double-word Shift Right instructions execute in two cycles. The high-order operand in
Ld is shifted first. At SARD and SHRD, the result is undefined if Ls denotes the same
register as Ld or Ldf.
Format Notation
Operation
insert
Rn
SARI Rd, n
Rd := Rd >> by n;
-- 0..31 sign bits
Ln
SARDI Ld, n
Ld//Ldf := Ld//Ldf >> by n;
-- 0..31 sign bits
LL
SAR Ld, Ls
Ld := Ld >> by Ls(4..0);
-- 0..31 sign bits
LL
SARD Ld, Ls
Ld//Ldf := Ld//Ldf >> by Ls(4..0);
-- 0..31 sign bits
Rn
SHRI Rd, n
Rd := Rd >> by n;
-- 0..31 zeros
Ln
SHRDI Ld, n
Ld//Ldf := Ld//Ldf >> by n;
-- 0..31 zeros
LL
SHR Ld, Ls
Ld := Ld >> by Ls(4..0);
-- 0..31 zeros
LL
SHRD Ld, Ls
Ld//Ldf := Ld//Ldf >> by Ls(4..0);
-- 0..31 zeros
The condition flags are set or cleared by all Shift Right instructions as follows:
Z := Ld = 0 or Rd = 0 on single-word;
Z := Ld//Ldf = 0 on double-word;
N := Ld(31) or Rd(31);
C := last bit shifted out is "one";
Note: The symbol >> signifies "shifted right".