GMS30C2216 Datasheet, PDF (137/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

BUS INTERFACE
6-21
6.5 Input Status Register ISR
Global register G25 is the read-only input status register ISR. The ISR reflects the input
levels at the pins IO1..IO3 as well as the input levels at the four interrupt pins INT1..INT4
and contains the EventFlag, the EqualFlag, the WatchdogFlag and the ClockOnFlag. Re-
served bits are read as.
The input levels are not affected by the polarity bits in the Function Control Register FCR,
they reflect always the true signal level at the corresponding pins with a latency of 2..3
cycles, a 1 signals high level.
Bits
31..11
10
Name
ClockOnFlag
9
WatchdogFlag
8
EventFlag
7
EqualFlag
6
IO3Level
5
IO2Level
4
IO1Level
3
Int4Level
2
Int3Level
1
Int2Level
0
Int1Level
Description
Reserved
Determines the source of the last reset event
1 = Last reset caused by a clock-down command
0 = Last reset caused by RESET# signal or watchdog timer
Determines the source of the last reset event
1 = Last reset caused by watchdog timer (IO3 timer)
0 = Last reset caused by RESET# signal or clock-down
command
Set to 1 in IO3Timing Mode when IO3Level is equal to
IO3Polarity
Cleared to 0 by FCR(13) = 1 or write to the WCR
Set to 1 in IO3Timing or IO3TimerInterrupt Mode when
WCR(15..0) = TR(15..0)
Cleared to 0 by FCR(13) = 1 or write to the WCR
Reflects the signal level at the IO3 Pin
1 = High Level
0 = Low Level
Reflects the signal level at the IO2 Pin
1 = High Level
0 = Low Level
Reflects the signal level at the IO1 Pin
1 = High Level
0 = Low Level
Reflects the signal level of interrupt input INT4
1 = High Level
0 = Low Level
Reflects the signal level of interrupt input INT3
1 = High Level
0 = Low Level
Reflects the signal level of interrupt input INT2
1 = High Level
0 = Low Level
Reflects the signal level of interrupt input INT1
1 = High Level
0 = Low Level
Table 6.7: Input Status Register ISR