GMS30C2216 Datasheet, PDF (74/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

3-12
CHAPTER 3
3.4 Logical Instructions
The result of a bitwise logical AND, AND not (ANDN), OR or exclusive OR (XOR) of the
source or immediate operand and the destination operand is placed in the destination
register and the Z flag is set or cleared accordingly. At ANDN, the source operand is used
inverted (itself remaining unchanged).
All operands and the result are interpreted as bitstrings of 32 bits each.
Format Notation
Operation
RR
AND Rd, Rs
Rd := Rd and Rs;
Z := Rd = 0;
-- logical AND
RR
ANDN Rd, Rs
Rd := Rd and not Rs;
Z := Rd = 0;
-- logical AND with source
used inverted
RR
OR Rd, Rs
Rd := Rd or Rs;
Z := Rd = 0;
-- logical OR
RR
XOR Rd, Rs
Rd := Rd xor Rs;
Z := Rd = 0;
-- logical exclusive OR
Rimm ANDNI Rd, imm
Rd := Rd and not imm;
Z := Rd = 0;
-- logical AND with imm
used inverted
Rimm ORI Rd, imm
Rd := Rd or imm;
Z := Rd = 0;
-- logical OR
Rimm XORI Rd, imm
Rd := Rd xor imm;
Z := Rd = 0;
-- logical exclusive OR
Note: ANDN and ANDNI are the instructions complementary to OR and ORI: Where OR
and ORI set bits, ANDN and ANDNI clear bits at bit positions with a "one" bit in the
source or immediate operand, thus obviating the need for an inverted mask in most cases.
Register
L0 : $0F0CFFFF
L1 : $FFFF0000
Instruction
AND L0, L1
ANDN
OR L0, L1
XOR L0, L1
ANDNI
; L0 = L0 and L1 = $0F0C0000
L0, L1
; L0 = L0 and not L1 = $0000FFFF
; L0 = L0 or L1 = $FFFFFFFF
; L0 = L0 xor L1 = $F0F3FFFF
L0, $1234 ; L0 = L0 and not imm = $0F0CEDCB
ORI L0, $1234 ; L0 = L0 or imm = $0F0CFFFF
XORI
L0, $1234 ; L0 = L0 xor imm = $0F0CEDCB