GMS30C2216 Datasheet, PDF (24/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

1-4
CHAPTER 1
All of these factors help RISC design approach their goal of executing one
cycle/instruction. However, two classes of instructions hinder achievement of this goal -
load instructions and branch instructions. The following sections discuss how RISC
designs overcome obstacles raised by these classes of instructions.
(3) Delayed Load Instructions
Load instruction read operands from memory into processor register for subsequent
operation by other instructions. Because memory typically operates at much slower speeds
than processor clock rates, the loaded operand is not immediately available to subsequent
instructions in an instruction pipeline. The data dependency is illustrated in Figure 1.3.
Load ₁
Instru c tio n
F
A
M
2F
A
3F
D ata from Load
W _{available as operatio n}
M
W
A
M
W
4F
A
M
W
Figure 1.3: Data Dependency Resulting From a Load Instruction
In this illustration, the operand loaded by instruction 1 is not available for use in the A
cycle (ALU, or Arithmetic/Logic Unit operation) of instruction 2. One way to handle this
dependency is to delay the pipeline by inserting additional clock cycles into the execution
of instruction 2 until the loaded data becomes available. This approach obviously
introduces delays that would increase the cycles/instructions factor.
In many RISC design the technique used to handle this data dependency is to recognize
and make visible to compilers the fact that all load instructions have an inherent latency or
load delay. Figure 3.3 illustrates a load delay or latency of one instruction. The instruction
that immediately follows the load is in the load delay slot. If the instruction in this slot does
not require the data from the load, and then no pipeline delay is required.
If this load delay is made visible to software, a compiler can arrange instructions to ensure
that there is no data dependency a load instruction and the instruction in the load delay slot.
The simplest way of ensuring that there is no data dependency is to insert a No Operation
(NOP) instruction to fill the slot, as follow:
Load
Load
NOP
ADD
R1, A
R2, B
<= This instruction fills the delay slot
R3, R1, R2
Although filling the delay slot with NOP instructions eliminates the need for hardware-
controlled pipeline stalls in this case, it still is not a very efficient use of the pipeline stream