GMS30C2216 Datasheet, PDF (76/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

3-14
CHAPTER 3
3.7 Add Instructions
The source operand, the source operand + C or the immediate operand is added to the
destination operand, the result is placed in the destination register and the condition flags
are set or cleared accordingly.
At ADD, ADDC and ADDI, both operands and the result are interpreted as either all
signed or all unsigned integers. At ADDS and ADDSI, both operands and the result are
signed integers and a trap to Range Error occurs at overflow.
Format Notation
Operation
RR
ADD Rd, Rs
Rd := Rd + Rs;
Z := Rd = 0;
N := Rd(31);
V := overflow;
C := carry;
-- signed or unsigned Add
-- sign
RR
ADDS Rd, Rs
Rd := Rd + Rs;
Z := Rd = 0;
N := Rd(31);
V := overflow;
if overflow then
trap ⇒ Range Error;
-- signed Add with trap
-- sign
RR
ADDC Rd, Rs
Rd := Rd + Rs + C;
Z := Z and (Rd = 0);
N := Rd(31);
V := overflow;
C := carry;
-- signed or unsigned Add
with carry
-- sign
When the SR is denoted as a source operand at ADD, ADDS and ADDC, C is added
instead of the SR. The notation is then:
Format Notation
Operation
RR
ADD Rd, C
Rd := Rd + C;
-- signed or unsigned Add C
RR
ADDS Rd, C
Rd := Rd + C;
-- signed Add C with trap
RR
ADDC Rd, C
Rd := Rd + C;
The flags and the trap condition are treated as defined by ADD, ADDS or ADDC.