GMS30C2216 Datasheet, PDF (25/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

ARCHITECTURE
1-5
since these additional NOP instructions increase code size and perform no useful work. (In
practice, however, this technique need not have much negative impact on performance.)
A more effective solution to handling the data dependency is to fill the load delay slot with
a useful instruction. Good optimizing compilers can usually accomplish this, especially if
the load delay is only one instruction. Below example program illustrates how a compiler
might rearrange instruction to handle a potential data dependency.
# Consider the code for C := A+B; F := D
Load R1, A
Load R2, B
Add R2, R1, R2
<= This instruction stalls because R2 data is not available
Load R4, D
.....
....
# An alternative code sequence (where delay length = 1)
Load R1, A
Load R2, B
Load R4, D
Add R3, R1, R2
<= No stall since R2 data is available
(4) Delayed Branch Instructions
Branch instructions usually delay the instruction pipeline because the processor must
calculate the effective destination of the branch and fetch that instruction. When a cache
access requires an entire cycle, and the fetched branch instruction specifies the target
address, it is impossible to perform this fetch (of the destination instruction) without
delaying the pipeline for at least one pipe stage (one cycle). Conditional branches can
cause further delays because they require the calculation of a condition, as well as the
target address.
Instead of stalling the instruction pipeline to wait for the instruction at the target address,
RISC designs typically use an approach similar to that used with Load instruction: Branch
instructions are delayed and do not take effect until after one or more instructions
immediately following the Branch instruction have been executed. The instruction or
instructions immediately following the Branch instruction (delay instruction) have been
executed. Branch and delayed branch instruction are illustrated in Figure 1.4
Condition ?
YES _{Branch Target}
NO
Next Instruction
Condition ?
Delay Instruction
YES
NO
Next Instruction
Delayed Branch
Branch Target
Branch Instruction
Delayed Branch Instruction
Figure 1.4: Block Diagram of Branch/Delayed Branch Instruction