GMS30C2216 Datasheet, PDF (127/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

BUS INTERFACE
6-11
6.2 I/O Bus Access
The bus timing for an I/O access is specified by bits 11..3 of the I/O address.
I/O Address
……
11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Wait Enable
Peri. Device Control Mode
0=IORD#/IOWR#
1=R/W#/DATA strobe control
Address Set-Up Time
00=0 Cycle
01=2 Cycle
10=4 Cycle
11=8 Cycle
Access Time
000=2 Cycle
001=4 Cycle
010=6 Cycle
011=8 Cycle
100=10 Cycle
101=12 Cycle
110=14 Cycle
111=16 Cycle
Bus Hold Time after Read/Write Access
00 = none
01 = 2 Cycle
10 = 4 Cycle
11 = 6 Cycle
On an I/O access, the I/O read strobe IORD# or the I/O write strobe IOWR# is switched
low for a read or write access respectively after the first access cycle and remains low for
the rest of the specified access cycles. The beginning of the IORD# or IOWR# signal can
be delayed by more than one cycle by specifying additional address setup cycles preceding
the access cycles. The beginning of the next bus access can be delayed by specifying bus
hold cycles succeeding the access cycles. Bus hold cycles are required by many I/O
devices due to the time required to switch from driving the data bus to three states.
Bit 11 of the I/O address enables a wait-pin controlled I/O access. The INT3/WAIT input
of the processor is sampled after the first three access cycles of the specified I/O access
time. The I/O access will be extended by inserting further access cycles as long as the sig-
nal at the WAIT input is asserted. When the WAIT signal becomes deasserted, the access
will be terminated. Note that there is latency of about 2..3 processor cycles until a signal
change at the WAIT input becomes effective. The polarity of the WAIT signal can be
programmed via bit 26 of the Function Control Register FCR. When FCR(26) is set to 1
(default after reset), the WAIT signal is high asserted; when FCR(26) is set to 0, the WAIT
signal is low asserted. A minimum of four I/O access cycles must be specified when the
I/O wait mode is being enabled.
When an I/O device requires R/W# direction and data strobe control, IORD# can be
specified (by address bit 10 = 1) as data strobe. WE# is then used as R/W# signal.