GMS30C2216 Datasheet, PDF (158/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

6-42
6.10.7.3 EDO DRAM Multi-Cycle Access
CHAPTER 6
CLK
Address Bus
high order bits
Address Bus
low order bits
RAS#
valid
undefin row addr.
Column address
Column address
CAS0#..CAS3#
RAS access RAS to CAS
time
delay time
1..6 cycles 1..4 cycles
CAS access time
1..6 cycles
CAS access time
1..6 cycles
WE#
at read access
OE#
Data Bus
(read data)
WE#
OE# is set after the first cycle of the CAS access time
at write access
OE#
Data Bus
(write data)
Figure 6.16: EDO DRAM Multi--Cycle Access