GMS30C2216 Datasheet, PDF (103/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

Instruction Set
3-41
3.33 Software Instructions
The Software instructions cause a branch to the subprogram associated with each Software
instruction. Its entry address (see section 2.4. Entry Tables), deduced from the OP-code of
the Software instruction, is placed in the program counter PC. Data is saved in the register
sequence beginning at register address FP + FL (FL = 0 is interpreted as FL = 16) in
ascending order as follows:
• Stack address of the destination operand
• High-order word of the source operand
• Low-order word of the source operand
• Old program counter PC, containing the return address and the old S flag in bit zero
• Old status Register SR, ILC contains the instruction-length code (ILC = 1) of the
software instruction
Then the frame pointer FP is incremented by the old frame length FL and FL is set to six,
thus creating a new stack frame. The cache-mode flag M and the trace-mode flag T are
cleared, the interrupt-lock flag L is set to one. All condition flags remain unchanged.
Instruction execution then proceeds at the entry address placed in the PC.
Ls or Lsf and Ld may denote the same register.
Format Notation
Operation
LL
see specific
instructions
PC := 23 ones//0//OP(11..8)//4 zeros;
(FP + FL)^ := stack address of Ld;
(FP + FL + 1)^ := Ls;
(FP + FL + 2)^ := Lsf;
(FP + FL + 3)^ := old PC(31..1)//old S;
(FP + FL + 4)^ := old SR;
FP := FP + FL;
-- FL = 0 is treated as FL = 16
FL := 6;
M := 0;
T := 0;
L := 1;
Note: At the new stack frame, the stack address of the destination operand can be
addressed as L0, the source operand as L1//L2, the saved PC as L3 and the saved SR as L4;
L5 is free for use as required.
A Frame instruction must be executed before executing any other Software instruction,
Trap or Call instruction or before the interrupt-lock flag L is being cleared, otherwise the
beginning of the register part of the stack at SP could be overwritten without any warning.