GMS30C2216 Datasheet, PDF (131/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

BUS INTERFACE
6-15
Bits Name
17..16 CASAccess
15..14 RasToCas
13..11 RefreshSelect
10..8 Mem3Hold
7
Mem3Setup
6..4 PageSizeCode
3
Mem2Setup
2..0 Mem2Hold
Description
CAS access time for address space MEM0
when MCR(8)=0
when MCR(8)=1
11 = 4 clock cycles
6 clock cycles
10 = 3 clock cycles
5 clock cycles
01 = 2 clock cycles
4 clock cycles
00 = 1 clock cycle
3 clock cycles
Ras to CAS delay time
11 = 4 clock cycles
10 = 3 clock cycles
01 = 2 clock cycles
00 = 1 clock cycle
Refresh rate select (CAS before RAS refresh)
111 = Refresh disabled
110 = Refresh every 4 prescaler time units
101 = Refresh every 8 prescaler time units
100 = Refresh every 16 prescaler time units
011 = Refresh every 32 prescaler time units
010 = Refresh every 64 prescaler time units
001 = Refresh every 128 prescaler time units
000 = Refresh every 256 prescaler time units
Bus hold time code for address space MEM3
111 = 7 clock cycles
110 = 6 clock cycles
101 = 5 clock cycles
100 = 4 clock cycles
011 = 3 clock cycles
010 = 2 clock cycles
001 = 1 clock cycle
000 = 0 clock cycles
Address setup time for address space MEM3
1 = 1 clock cycle
0 = 0 clock cycles
Page size code
Address setup time for address space MEM2
1 = 1 clock cycle
0 = 0 clock cycles
Bus hold time code for address space MEM2
111 = 7 clock cycles
110 = 6 clock cycles
101 = 5 clock cycles
100 = 4 clock cycles
011 = 3 clock cycles
010 = 2 clock cycles
001 = 1 clock cycle
000 = 0 clock cycles
Table 6.4: Bus Control Register BCR