GMS30C2216 Datasheet, PDF (112/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

4-2
CHAPTER 4
4.2 Exception Types
The following exceptions are types ordered by priorities, Reset has the highest priority. In
case of coincidental exceptions, higher-priority exceptions overrule lower-priority
exceptions.
4.2.1 Reset
A Reset exception occurs on a transition of the RESET# signal from low to high or as a
result of a watchdog overrun in IO3 Watchdog mode or after a reset following a clock-
down command. The Reset exception overrules all other exceptions and is used to start
execution at the Reset entry.
The load and store pipelines are cleared. The BCR, MCR, FCR and TPR initialization in
the three reset cases is specified in the table 4.1; all other registers and flags, except those
set or cleared explicitly by the exception processing itself, remain undefined and must be
initialized by software.
In the reset handler, ISR bits 9 and 10 can be used to discriminate between the three reset
sources.
Reset source
RESET#
Watchdog
Clock-Down
BCR
initialized
initialized
initialized
MCR
initialized
initialized
initialized
FCR
initialized
initialized
preserved
TPR
initialized
preserved
initialized
Table 4.1: Memory Address Spaces
The FCR is preserved on a clock-down reset in order to have the correct interrupt mask and
polarity for the wakeup from clock-down. TPR is preserved on a watchdog reset to allow
the use of the watchdog reset as a controlled time-out without losing the time base. The
other registers are initialized to their specific reset value.
Note: The frame pointer FP can only be set to a defined value by restoring it from the FP in
the return SR through a Return instruction.
4.2.2 Range, Pointer, Frame and Privilege Error
These exceptions share a common entry since they cannot occur coincidentally at the same
instruction. The error-causing instruction can be identified by backtracking.
A Range Error exception occurs when an operand or result exceeds its value range.
A Pointer Error is caused by an attempted memory access using an address register (Rd or
Ld) with the content zero. The memory is not accessed, but the content of the address
register is updated in case of a postincrement or next address mode.
A Frame Error occurs when the restructuring of the stack frame reaches or exceeds the
upper bound UB of the memory part of the stack. No further Frame instruction must be
executed by the error routine for Pointer, Frame and Privilege Error before the UB is set to
a higher value and thus, an expanded stack frame fits into the higher stack bound.
A Privilege Error occurs when a privileged operation is executed in user or on return to
user state (see section 1.5. Privilege States for details).