GMS30C2216 Datasheet, PDF (313/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

Appendix A. Instruction Set Details
Signed Sum with Trap
A-141
SUMS
Format:
RRconst format
15
OP-code 0001 11
eS
87
43
0
ds
Rd-code
Rs-code
const1
cosnt2
s = 0: Rs-code encodes G0..G15 for Rs, s = 1: Rs-code encodes L0..L15 for Rs
d = 0: Rd-code encodes G0..G15 for Rd, d = 1: Rd-code encodes L0..L15 for Rd
S : Sign bit of dis, e = 0: const = 18S // const1 (range -16,384..16,383)
e = 1: const = 2S // const1 // const2 (range -1,073,741,824...1,073,741,823)
Notation:
SUMS Rd, Rs, const
SUMS Rd, C, const
(When SR is denoted as a source operand)
Description:
The sum of the source operand is placed in the destination register and the condition flags
are set or cleared accordingly.
Both operands and the result are interpreted as all signed integers and a trap to Range Error
occurs at overflow.
When the SR is denoted as a source operand, C is added instead of the SR.
Operation:
When Rs does not denote SR
Rd := Rs + const;
Z := Rd = 0;
N := Rd(31);
V := overflow;
If overflow then
trap => Range Error
When Rs denotes SR
Rd := C + const;
Z := Rd = 0;
N := Rd(31);
V := overflow;
If overflow then
trap => Range Error
Exceptions:
Overflow (Trap to Range Error).