GMS30C2216 Datasheet, PDF (30/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

1-10
CHAPTER 1
The status register SR contains the following status information:
C
Carry Flag. Bit zero is the carry condition flag C. In general, when set it
indicates that the unsigned integer range is exceeded (overflow). At add
operations, it indicates a carry out of bit 31 of the result. At subtract operations,
it indicates a borrow (inverse carry) into bit 31 of the result.
Z
Zero Flag. Bit one is the zero condition flag Z. When set, it indicates that all 32
or 64 result bits are equal to zero regardless of any carry, borrow or overflow.
N
Negative Flag. Bit two is the negative condition flag N. On compare
instructions, it indicates the arithmetic correct (true) sign of the result
regardless of an overflow. On all other instructions, it is derived from result bit
31, which is the true sign bit when no overflow occurs. In the case of overflow,
result bit 31 and N reflect the inverted sign bit.
V
Overflow Flag. Bit three is the overflow condition flag V. In general, when set
it indicates a signed overflow. At the Move instructions, it indicates a floating-
point NaN (Not a Number).
M
Cache-Mode Flag. Bit four is the cache-mode flag M. Besides being set or
cleared under program control, it is also automatically cleared by a Frame
instruction and by any branch taken except a delayed branch. See section
1.8. Instruction Cache for details.
H
High Global Flag. Bit five is the high global flag H. When H is set, denoting
G0..G15 addresses G16..G31 instead. Thus, the registers G18..G27 may be
addressed by denoting G2..G11 respectively.
The H flag is effective only in the first cycle of the next instruction after it was
set; then it is cleared automatically.
Only the MOV or MOVI instruction issued as the next instructions must be
used to copy the content of a local register or an immediate value to one of the
high global registers. The MOV instruction may be used to copy the content of
a high global register (except the BCR, TPR, FCR and MCR register, which
are write-only) to a local register. With all other instructions, the result may be
invalid.
If one of the high global registers is addressed as the destination register in user
state (S = 0), the condition flags are undefined, the destination register remains
unchanged and a trap to Privilege Error occurs.
Reserved Bit six is reserved for future use. It must always be zero.
I
Interrupt-Mode Flag. Bit seven is the interrupt-mode flag I. It is set
automatically on interrupt entry and reset to its old value by a Return
instruction. The I flag is used by the operating system; it must be never
changed by any user program.
FTE
Floating-Point Trap Enable Flag. Bits 12..8 are the floating-point trap enable
flags They determine the Exception type and Trap execution flow(see section
3.33.2. Floating-Point Instructions).
FRM
Floating-Point Rounding Mode. Bits 14..13 are the floating-point rounding
modes (see section 3.33.2. Floating-Point Instructions).