GMS30C2216 Datasheet, PDF (12/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

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CHAPTER 0
• An instruction pipeline depth of only two stages —decode/execute —provides
branching without insertion of wait cycles in combination with Delayed Branch
instructions.
• Range and pointer checks are performed without speed penalty, thus, these checks need
no longer be turned off, thereby providing higher runtime reliability.
• Separate address and data buses provide a throughput of one 32-bit word each cycle.
The features noted above contribute to reduce the number of idle wait cycles to a bare
minimum. The processor is designed to sustain its execution rate with a standard DRAM
memory.
The low power consumption is of advantage for mobile (portable) applications or in
temperature-sensitive environments.
Most of the transistors are used for the on-chip memory, the instruction cache, the register
stack and the multiplier, whereas only a smallnumber is required for the control logic.
Due to their low system cost, the GMS30C2216 and GMS3OC2232 RISC/DSP are very
well suited for embedded-systems applications requiring high performance and lowest cost.
To simplify board design as well as to reduce system costs, the GMS30C2216 and
GMS30C2232 already come with integrated periphery, such as a timer and memory and
bus control logic. Therefore, complete systems with the HME’s microprocessor can be
implemented with a minimum of external components. To connect any kind of memory or
I/O, no glue logic is necessary. It is even suitable for systems where up to now
microprocessors with 16-bit architecture have been used for cost reasons. Its improved
performance compared to conventional microcontrollers can be used to software-substitute
many external peripherals like graphics controllers or DSPs.
The software development tools include an optimizing C compiler, assembler, source-level
debugger with profiler as well as a real-time kernel with an extremely fast response time.
Using this real-time kernel, up to 31 tasks, each with its own virtual timer, can be
developed independently of each other. The synchronization of these tasks is effected
almost automatically by the real-time kernel. To the developer, it seems as if he has up to
31 HME’s microprocessors to which he can allocate his programs accordingly. Real-time
debugging of multiple tasks is assisted in an optimized way.
The following description gives a brief architectural overview:
Compatibility:
• Pin compatible to HME GMS30C2116/32, and hyperstone E1-16/32
• Pin and Function Compatible to hyperstone E1-16/32X
PLL(Phased Locked Loop):
• An internal phased locked loop circuit (PLL) provides clock rate multiplication by a
factor of four, only an external crystal of 27MHz is required to achieve an internal clock
rate of 108MHz.