GMS30C2216 Datasheet, PDF (136/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

6-20
CHAPTER 6
6.4.6 IRAM Refresh Rate
Bits 18..16 of the MCR specify the IRAM refresh rate in number (4..256) of prescaler
time units. The default setting is disabled. Recommended refresh rate for normal IRAM
usage is every 2 prescaler time units.
6.4.7 DRAM Type
When the MEM0 memory type is set to DRAM (MCR(21)=0), bit 15 of the MCR acts as
control bit for selecting the DRAM type. The default setting is Fast-Page-Mode DRAM.
To support EDO DRAMs, MCR(15) must be cleared.
When the DRAM type indicates Fast-Page-Mode DRAMs, the OE# signal of the processor
is left disserted during DRAM accesses. The OE# pin of the DRAMs must then be tied low
for correct DRAM operation.
When the DRAM type indicates EDO DRAMs, OE# must be connected to the DRAMs
and is asserted on DRAM read accesses. OE# stays active for one half clock cycle past the
end of the CAS# signals, the read data is sampled at the end of OE#. Thus, the processor
can take advantage of the EDO fracture.
6.4.8 Entry Table Map
Bits 14..12 of the MCR map the entry table to one of the memory areas MEM0..MEM3 or
to the IRAM. With a mapping to MEM3 (default setting), the entry table is mapped to the
end of MEM3, with all other settings, the entry table is mapped to the beginning of the
specified memory area.
6.4.9 MEMx Bus Hold Break
Bits 11..8 specify a memory bus hold break for MEM3..MEM0 respectively. The default
setting is disabled. With enabled, bus hold cycles are skipped when the next memory access
addresses the same memory area. Regularly, the bus hold break should be enabled; it must
only be left disabled to accommodate (rare) SRAMs or ROMs which need all specified
cycles before a new access can be started (e.g. for charge restore).
If the MEM0 memory type is DRAM, bit 8 changes the RasPrecharge and CASAccess
cycle counts specified in BCR, and specifies a bus hold time of 0 or 1 cycle. Bus hold
break for DRAM is always enabled.
6.4.10 MEMx Bus Size
Bits 7..0 specify the bus size for each of the four memory areas