GMS30C2216 Datasheet, PDF (84/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

3-22
CHAPTER 3
3.14 Shift Left Instructions
The destination operand is shifted left by a number of bit positions specified
at SHLI, SHLDI by n = 0..31 as a shift by 0..31;
at SHL, SHLD by bits 4..0 of the source operand as a shift by 0..31.
The higher-order bits of the source operand are ignored.
The destination operand is interpreted
at SHL and SHLI as a bitstring of 32 bits or as a signed or unsigned integer;
at SHLD and SHLDI as a double-word bitstring of 64 bits or as a signed or
unsigned double-word integer.
All Shift Left instructions insert zeros in the vacated bit positions at the right.
The double-word Shift Left instructions execute in two cycles. The low-order operand in
Ldf is shifted first. At SHLD, the result is undefined if Ls denotes the same register as Ld
or Ldf.
Format Notation
Operation
insert
Rn
SHLI Rd, n
Rd := Rd << by n;
-- 0..31 zeros
Ln
SHLDI Ld, n
Ld//Ldf := Ld//Ldf << by n;
-- 0..31 zeros
LL
SHL Ld, Ls
Ld := Ld << by Ls(4..0);
-- 0..31 zeros
LL
SHLD Ld, Ls
Ld//Ldf := Ld//Ldf << by Ls(4..0);
-- 0..31 zeros
The condition flags are set or cleared by all Shift Left instructions as follows:
Z := Ld = 0 or Rd = 0 on single-word;
Z := Ld//Ldf = 0 on double-word;
N := Ld(31) or Rd(31);
V := undefined
C := undefined;
Note: The symbol << signifies "shifted left".
Register
L0 : $FFFF
L1 : $2
Instruction
SHLI
SHL L0, L1
L0, $4
; L0 = $000FFFF0
; L0 = $0003FFFC