GMS30C2216 Datasheet, PDF (133/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

BUS INTERFACE
6-17
6.4 Memory Control Register MCR
Global register G27 is the write-only memory control register MCR. The MCR controls
additional parameters for the external memory, the internal memory refresh rate, the
mapping of the entry table and the processor power management. All bits of the MCR are
set to one on Reset except for the MEM3BusSize bits that are initialized from the BOOTW
and BOOTB pads. The MCR bits must be initialized according to the hard ware
environment and the desired function.
Bits
31
30
29
28
27
26
25
24
23
22
21
20
19
18..16
Name
MEM3ParityDisable
MEM2ParityDisable
MEM1ParityDisable
MEM0ParityDisable
MEM2WaitDisable
MEM2ByteMode
MEM0MemoryType
IRAMRefreshTest
MEM1ByteMode
IRAMRefreshRate
Description
Parity check disable for address space MEM3
1 = disabled
0 = enabled
Parity check disable for address space MEM2
1 = disabled
0 = enabled
Parity check disable for address space MEM1
1 = disabled
0 = enabled
Parity check disable for address space MEM0
1 = disabled
0 = enabled
Reserved
Wait signal disable for address space MEM2
1 = disabled
0 = enabled
Reserved
Reserved
Byte write access mode for address space MEM2
1 = WE0# .. WE3# act as byte write strobe
0 = WE0# .. WE3# act as byte enable signal
Reserved for internal use
1 = Non-DRAM
0 = DRAM
1 = Normal Mode
0 = Test Mode
Byte write access mode for address space MEM1
1 = WE0# .. WE3# act as byte write strobe
0 = WE0# .. WE3# act as byte enable signal
111 = Disabled
110 = Refresh every 2 prescaler time units (recommended)
101 = Refresh every 4 prescaler time units
100 = Refresh every 8 prescaler time units
011 = Refresh every 16 prescaler time units
010 = Refresh every 32 prescaler time units
001 = Refresh every 64 prescaler time units
000 = Refresh every 128 prescaler time units