GMS30C2216 Datasheet, PDF (62/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

3-14
CHAPTER 3
Extended DSP instruction and the first instruction using the result. When less than the
number of latency cycles are used by these instructions, the execution of the instruction
using the result is delayed until the result is available in G15 or G14//G15.
When an Extended DSP instruction that uses the internal hardware multiplier (EMUL, ...,
EHCMACD) succeeds an Extended DSP instruction that also uses the internal hardware
multiplier after less than latency - 1 cycles, the issue of the succeeding Extended DSP
instruction is delayed until latency - 1 cycles are finished. An Extended DSP instruction
succeeding the EHCSUMD or EHCFFTD instruction after less than the latency cycles for
these two instructions is always delayed until the EHCSUMD or EHCFFTD instruction is
finished.
The latency cycles are as follows:
EMUL instruction:
when both operands are in the range of -2¹⁵..2¹⁵-1: 1 cycle
all other cases: 3 cycles
EMULU instruction:
when both operands are in the range of 0..2¹⁶-1: 2 cycles
all other cases: 4 cycles
EMULS instruction:
when both operands are in the range of -2¹⁵..2¹⁵-1: 3 cycles
all other cases: 4 cycles
EMAC instruction:
when both operands are in the range of -2¹⁵..2¹⁵-1: 2 cycles
all other cases: 3 cycles
EMACD instruction:
when both operands are in the range of -2¹⁵..2¹⁵-1: 3 cycles
all other cases: 4 cycles
EMSUB instruction:
when both operands are in the range of -2¹⁵..2¹⁵-1: 2 cycles
all other cases: 3 cycles
EMSUBD instruction:
when both operands are in the range of -2¹⁵..2¹⁵-1: 3 cycles
all other cases: 4 cycles
EHMAC instruction: 2 cycles
EHMACD instruction: 4 cycles
EHCMULD instruction: 4 cycles
EHCMACD instruction: 4 cycles
EHCSUMD instruction: 2 cycles
EHCFFTD instruction: 2 cycles