GMS30C2216 Datasheet, PDF (46/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

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CHAPTER 1
At an explicit Branch or Delayed Branch instruction (except when placed as delay
instruction) with an instruction length of one halfword, the location of the branch target is
checked. The branch target is treated as being in the cache when the target address of a
backward branch is not lower than the address in the look-back counter and the target
address of a forward branch is not higher than two words above the address in the look-
ahead counter. That is, the two instruction words succeeding the instruction word
addressed by the content of the look-ahead counter are treated by a forward branch as
being in the cache. Their actual fetch overlaps in most cases with the execution of the
branch instruction and thus, no cycles are wasted. When the branch target is in the cache,
the look-back counter and the look-ahead counter remain unchanged.
When a branch is taken by a Delayed Branch instruction with an instruction length of one
halfword to a forward branch target not in the cache and the cache mode flag M is enabled
(1), the look-back counter and the look-ahead counter remain unchanged. Wait cycles are
then inserted until the ongoing prefetch has loaded the branch target instruction into the
cache.
Any other branch taken flushes the cache by placing the branch address in the look-back
and the look-ahead counter. Prefetch then starts immediately at the branch address.
Instruction decoding waits until the branch target instruction is fully available in the cache.
The cache mode flag M (bit four of the SR) can be set or cleared by logical instructions. It
is automatically cleared by a Frame instruction and by any branch taken except a branch
caused by a Delayed Branch or Return instruction; a Delayed Branch instruction leaves the
M flag unchanged and a Return instruction restores the M flag from the saved status
register SR.
Note: Since up to eight instruction words can be loaded into the cache by the prefetch, only
24 instruction words are left to be contained in a program loop. Thus, a program loop can
have a maximum length of 96 or 94 bytes including the branch instruction closing the loop,
depending on the even or odd halfword address location of the first instruction of the loop
respectively.
A forward Branch or Delayed Branch instruction with an instruction length of one
halfword into up to two instruction words succeeding the word addressed by the look-
ahead counter treats the branch target as being in the cache and does not flush the cache.
Thus, three or four instruction halfwords, depending on the odd or even halfword address
location of the branch instruction respectively, can always be skipped without flushing the
cache.
Enabling the cache-mode flag M is only required when a program loop to be contained in
the cache contains a forward branch to a branch target in the program loop and more than
three (or four, see above) instruction halfwords are to be skipped. In this case, the enabled
M flag in combination with a Delayed Branch instruction with an instruction length of one
halfword inhibits flushing the cache when the branch target is not yet prefetched.