GMS30C2216 Datasheet, PDF (149/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

BUS INTERFACE
6-33
6.10.1.3 SRAM and ROM Multi-Cycle Read Access
CLK
Chip Select
Address Bus
WE#
WE0#..WE3#
OE#
Data Bus
Address setup
time 0..3 cycles
Access time
2..16 cycles
Bus hold
time
0..7 cycles
Figure 6.4: SRAM and ROM Multi-Cycle Read Access, MEMx Byte Mode = 1
6.10.1.4 SRAM Multi-Cycle WriteAccess
CLK
Chip Select
Address Bus
WE#
WE0#..WE3#
OE#
Data Bus
Address setup
time 0..3 cycles
Access time
2..16 cycles
Figure 6.5: SRAM Multi-Cycle Write Access, MEMx Byte Mode = 1
Bus hold
time
0..7 cycles