GMS30C2216 Datasheet, PDF (154/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

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6.10.5 I/O Read Access with WAIT Pin
CHAPTER 6
address setup time = 0 cycles, bus hold time = 0 cycles, INT3Polarity =
CLK
Chip Select
Address Bus
WE#
WAIT
OE#
Data Bus
Access time
(minimum 4 cycle)
Figure 6.12: I/O Read Access with WAIT Pin
Next access
or bus hold
time if specified
Note:
• Arrows on WAIT signal indicate the times where the signal is inspected.
• In this example
specified access time: 4 cycles
actual access time: 6 = 4 cycles + 2 additional cycles caused by WAIT pin