GMS30C2216 Datasheet, PDF (113/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

Exceptions
4-3
4.2.3 Extended Overflow
An Extended Overflow condition is raised on an overflow caused by an add or subtract
operation as part of the execution of one of the Extended instructions EMAC through
EHCFFTD when the Extended Overflow exception is enabled. The Extended Overflow
exception is enabled by clearing bit 16 of the function control register FCR to zero.
When the Extended Overflow exception is blocked by a higher-priority exception or by the
L flag being set, the Extended Overflow condition is saved internally; the exception trap
occurs then when the blocking is released.
The Extended Overflow condition is cleared by the exception trap or by setting FCR(16) to
one (disabled).
The Extended Overflow exception trap occurs asynchronously to the causing instruction;
thus, the causing instruction cannot be identified by backtracking. Usually, there is only
one instruction in a loop that can cause an Extended Overflow exception; thus, a handler
can identify that instruction. When a second Extended Overflow condition is raised before
the first one caused a trap, it is ored and only one trap is taken.
4.2.4 Parity Error
A Parity Error exception can be enabled individually for each of the memory areas
MEM0..MEM3. When enabled, a parity error on an access to the corresponding memory
area causes a Parity Error exception.
When the Parity Error exception is blocked by a higher-priority exception or by the L flag
being set, the Parity Error condition is saved internally, the exception trap occurs then
when the blocking is released.
The Parity Error condition is cleared only by the exception trap; it is not cleared by setting
any of the disable bits 31..28 in the BCR after a Parity Error condition is saved internally.
The Parity Error exception trap occurs asynchronously to the causing memory instruction.
Since memory accesses are pipelined, a Parity Error exception cannot be related to a
specific memory instruction.
4.2.5 Interrupt
An Interrupt exception is caused by an external interrupt signal, by the timer interrupt or by
an IO3 Control Mode. Since the interrupt-lock flag L is set by the exception processing, no
further interrupts can occur until the L flag is cleared. The interrupt exception processing
sets also the interrupt-mode flag I to one. See also sections 2.4. Entry Tables, 5. Timer and
6.9. Bus Signals.
The I flag is used by the operating system, it must not be cleared by the interrupt handler.
A Return instruction restores the old value from the saved SR automatically.